1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a physical structure of a static-type semiconductor memory device.
2. Description of the Prior Art
Generally, a static-type semiconductor memory device comprises word lines, pairs of bit lines, power supply lines, and ground lines formed on an insulating layer, on a semiconductor substrate. At each cross point of these word lines and these pairs of bit lines, a static-type memory cell consisting of metal-insulator semiconductor (MIS) transistors is arranged. Each MIS transistor has a gate electrode which is in contact with a gate-electrode wiring line.
Conventionally, the word lines, the power supply lines, and the gate-electrode wiring lines are formed by a first conductive layer of, for example, polycrystalline silicon, and extend parallel to each other, the first conductive layer being formed, through an insulating layer, on a semiconductor substrate. The pairs of bit lines and the ground lines are formed by a second conductive layer of, for example, aluminum, and extend in a direction perpendicular to the direction of the word lines the second conductive layer being formed on an insulating layer on the first conductive layer. Accordingly, for each memory cell, there are four polycrystalline-silicon wiring lines in a row direction, i.e., a word line, a power supply line, and two gate-electrode wiring lines for two MIS transistors cross-coupled with each other; and there are three aluminum wiring lines in a column direction, i.e., a pair of bit lines and a ground line.
To improve the yield in manufacturing semiconductor memory devices or to improve the degree of integration of a semiconductor memory device, it is preferable that the number of lines, formed by one conductive layer and extending in one direction, be as small as possible to promote easy wiring. Also, in order to achieve higher speed access to a memory cell, it is preferable to use material having a high electrical conductivity for the word lines, pairs of the bit lines, and power supply lines.
In the conventional structure, however, since there are four polycrystalline-silicon lines in the row direction and three aluminum lines in the column direction, for each memory cell, there is a limit to the attainable ease of wiring, yield, and integration degree. Also, in the conventional structure, since the word lines and the power supply lines as well as the gate electrode wiring lines are simultaneously formed using the same conductive layer of polycrystalline silicon and since the resistivity of polycrystalline silicon is higher than that of good conducting material such as aluminum, high speed access is prevented.
From another point of view, recent advances in increasing the integration degree of semiconductor memory devices have resulted in a corresponding decrease in the amount of charge an individual memory cell can store. Therefore, countermeasures for soft errors due to alpha particles have become necessary not only for dynamic-type semiconductor memory devices, but also static-type semiconductor memory devices. Conventionally, static-type semiconductor memory devices have not been provided with countermeasures against soft errors due to alpha particles.